Large-Scale Power Combining and Mixed-Signal Linearizing Architectures for Watt-Class mmWave CMOS Power Amplifiers

Efficient Watt-Level Power Amplifiers in Deeply Scaled CMOS

Advances in silicon processing technology have made CMOS power amplifiers a feasible option for wireless communication applications. Compared to the compoundsemiconductor counterparts, CMOS PAs become increasingly attractive due to their lower cost and higher level of integration. The continued scaling of CMOS technology further extends the cut-off frequency of CMOS devices up to several hundre...

Low-Power Adder Design for Nano-Scale CMOS

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

CMOS-MEMS Enhanced Power Amplifiers

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FPGA Implementation of a Hammerstein Based Digital Predistorter for Linearizing RF Power Amplifiers with Memory Effects

Power amplifiers (PAs) are inherently nonlinear elements and digital predistortion is a highly cost-effective approach to linearize them. Although most existing architectures assume that the PA has a memoryless nonlinearity, memory effects of the PAs in many applications ,such as wideband code-division multiple access (WCDMA) or orthogonal frequency-division multiplexing (OFDM), can no longer b...

CMOS Power Amplifiers for Wireless Communications